Senior Verification Engineer

<h3> General Information </h3> Job Title Senior Verification Engineer Job ID 9899 Country Germany City Aschheim/Dornach Date Posted 04-Mar-2025 Job Category Engineering Job Subcategory R&amp;D Engineering Hire Type Employee Remote Eligible Yes <h3> Descriptions &amp; Requirements </h3> Job Description and Requirements <p><span>      At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</span></p><p><span><br/><br/><strong><span>Who are we looking for:</span></strong><br/><br/></span><span id="isPasted">     Senior Verification Engineer to contribute to the design verification of Register Transfer Level (RTL) based Intellectual Property (IP) Cores, encompassing intricate protocols. This position is located within the Intellectual Property Group at Synopsys, where the successful candidate will be instrumental in the creation of design verification solutions for IP utilized within Automotive end-customer applications. This role involves collaboration with our global team of architects, designers, and verification team members across multiple international sites. The position provides opportunities for professional development and growth. As a Senior Technical Individual Contributor, this role presents the challenge of working on technically demanding IP Cores in the Verification domain.</span><span><br/></span><span><br/></span><span id="isPasted"><strong><span>What are the requirements for the role:</span></strong></span><span><br/></span></p><ul id="isPasted"><li><span>Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science</span></li><li><span>4 to 8 years of experience in IP/SOC Verification domains and have working knowledge of industry standard EDA tools </span></li><li><span>Advanced knowledge of Verilog, System Verilog</span></li><li><span>Experience with debugging of designs in simulation. </span></li><li><span>Hands on experience in creating Test Environment from Functional Specifications using UVM/VMM/OVM, Test Plan