Senior Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate should be a self-starter who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Responsibilities

The AISiE silicon team is seeking a Senior Design Verification Engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Internet protocol(IP) and System on Chip(SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.

• Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology(UVM), or formally verify designs with SystemVerilog Assertions(SVA) and industry leading formal tools.
• Develop tests using UVM or C/C++.
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage to plug verification holes and meet tape out requirements.
• Other
  • Embody our Culture and Values 

Qualifications

Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 6+ years of experience in design verification with a proven track record of delivering complex Central Processing Unit(CPU) or SoC IP’s.
• Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
• Background in debugging Register Transfer Level(RTL) Verilog designs as well as simulation and/or emulation environments.
• Experience in Scripting language such as Python or Perl.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Good understanding of computer architecture.
• Hands on experience in Formal property verification.
• Processor based testbenches and emulation.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the b