Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

·       Life at Intel

·       Diversity at Intel

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge.   As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you.

As a Physical Design Engineer in the Network and Edge group your responsibilities will be as below:

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

 

Qualifications:

What we need to see (Minimum Qualifications):

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor's degree in Electrical Engineering, Computer Engineering or in a related field of study and 6+ years of relevant experience OR a Master's degree in in Electrical Engineering, Computer Engineering, or in a related field of study and 5+ years of relevant experience OR PhD in in Electrical Engineering, Computer Engineering or in a related field of study and 2+ years of related experience.   
• 4+ years of experience in VLSI design, preferably in a tools and methodology development role.
• 2+ years' experience programming in Perl or Python or Shell scripting, TCL.
• 2+ years' experience in digital ASIC design flow and methodology.
• 2+ years' experience in EDA tools such as Cadence or Synopsys or Mentor Graphics.

How to Stand out (Preferred Qualifications):

• Master's degree in in Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study and 6+ years of relevant experience OR PhD in in Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study and 4+ years of relevant experience
• 6+ years' experience with low power, high-speed, or mixed-signal design methodologies.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.  Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, San Jose

Additional