Senior UVM Digital Verification Engineer

Overview:

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.

Job Description Summary:

Draper’s Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

Job Description:

Duties/Responsibilities
• Performs analysis approaches for a particular problem and independently execute assignments.
• Independently execute system engineering lifecycle assignments; concept and architecture design, integration, testing and operation.
• Drive solutions to complex problems with limited direction – contribute to task planning and test development, propose ways forward, and adapt appropriately to changes in program requirements
• Demonstrated ability to lead small teams (fewer than five people). Seeks to align team towards program goals and builds trust within the team.
• Able to provide insight and suggest design modifications based on analysis outcomes, and to apply analysis techniques across a range of technical challenges.
• Identify program/system-level technical risks and develop and execute mitigation strategies for them.
• Actively mentor less experienced engineers and provide thoughtful, constructive feedback.
• Work in a collaborative multidisciplinary environment including stakeholders and external partners.
• Contribute to translation of requirements into technical and architectural decisions.

Skills/Abilities
• Excellent mathematical skills.
• Thorough understanding of engineering theories and procedures.
• Ability to collaborate within a diverse and multidisciplinary team.
• Excellent verbal and written communication skills.
• Excellent organizational skills and attention to detail.
• Excellent time management skills with the proven ability to meet deadlines.
• Demonstrated knowledge of multiple problem domains, with ability to quickly become knowledgeable in new domains.
• Identify and develop relevant modeling and analysis techniques, and develop or integrate multi-domain qualitative models.
• Ability to present results that support system-level analysis, performance trade-offs, and decision-making is critical, thus communications and interpersonal skills are highly valued in this role.
• The ability to communicate technical concepts effectively with customers, engineers, managers, and other stakeholders of all relevant disciplines.
• Flexibility to multi-task and adapt to evolving priorities.

Education
Bachelor’s degree in Aerospace, Electrical, Mechanical, or other relevant Engineering field. Master's degree preferred.

Experience
• Requires 5-7 years experience in systems analysis or related.
• Experience in use of MBSE tools such as SysML, knowledge in MATLAB/Simulink.
• Experience in integrating descriptive modeling tools with other simulation tools.

Additional Job Description:

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

• Develop verification and test plans
• Develop UVM Agents for proprietary buses  
• Instantiate VIPs for industry standard buses
• Work in both block-level/chip-level UVM testbench environment
• Work with RTL designers to resolve simulation issues   
• Implement cover groups according to design requirements
• Work on code and functional coverage closures to achieve 100%
• Perform code reviews and to mentor junior engineers in the group
• Fluent in System Verilog including SVA
• Recent experience with UVM/UVMF
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