Senior Design Verification Engineer – High Performance CPU Core

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

The Role

SiFive is looking for a Senior Design Verification Engineer to drive functional verification of high-performance CPU core units.

This role focuses on high-performance out-of-order core verification, with potential scope across areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch.

You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is verified correctly, risks are identified early, and signoff quality is achieved with strong technical execution.

We are looking for an engineer who can independently own meaningful verification work, solve complex debug problems efficiently, and contribute reusable methodology and infrastructure to the broader CPU DV team.

Responsibilities

• Own verification planning and execution for assigned high-performance CPU core areas, from block-level verification through core-level integration.

• Create effective verification strategies and test plans based on CPU architecture and microarchitectural behavior.

• Develop and maintain robust verification environments, testbenches, checkers, scoreboards, assertions, stimulus, and coverage models.

• Define and execute directed and constrained-random tests that expose corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch behavior, hazard handling, load/store ordering, memory consistency, and hardware prefetch behavior.

• Analyze failures, isolate root cause, and drive fixes across RTL, testbench infrastructure, assertions, and test content.

• Collaborate closely with architecture and design teams to review specifications, identify ambiguities early, and improve verification quality and debugability.

• Write functional coverage, analyze code and functional coverage, and close coverage gaps to ensure verification completeness and signoff quality.

• Contribute to reusable DV methodology, automation, and infrastructure that improve team productivity and verification quality across future core generations.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 3+ years of relevant experience in IP, CPU/core, or SoC functional verification, preferably with experience in CPU/core verification.

• Strong hands-on experience with SystemVerilog and UVM-based verification methodologies.

• Solid understanding of computer architecture and CPU microarchitecture fundamentals.

• Experience with test planning, testbench development, constrained-random verification, failure analysis, coverage analysis, and coverage closure.