NAND Memory Package R&D Engineer

Company Description

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

Job Description

Solidigm is seeking an innovative NAND Memory Package Integration Engineer to support the pathfinding and development of package technologies for Solid State Drive (SSD). In this role, you’ll be responsible for pioneering packaging technologies to align with the SSD product roadmap. You’ll work with the wafer fab and Assembly Test Subcon in process integration & development. Other responsibilities include driving and tracking package design milestones, integrating product requirements into packaging solutions, identifying and resolving packaging design issues, and communicating design status.

Qualifications

• BS Physics, Chemistry, Chemical, Mechanical, Electrical, Material Science or other Engineering discipline
• 5-10 years of experience in semiconductor package development
• Knowledge in Silicon thin film processing and understanding of the interactions between silicon and Microelectronics package manufacturing
• Familiar with Silicon layout design
• Proficient in failure analysis at both silicon and package levels (EFA, PFA), design of experiments, and data analysis
• Proven abilities in program management, communication, teamwork, planning, and prioritization

Preferred Skills:

• Solid understanding of package substrate design from a signal integrity perspective
• Proficient with HSPICE, Ansoft Q2D/Q3D, or other field solvers
• Skilled in high-speed signal integrity, power delivery, and DDR package design
• Familiar with PCB assembly and package-to-board interconnects
• Knowledgeable about flip chip packaging
• Experience with AutoCAD and Cadence (APD, Editor, SIP)

Additional Information

The compensation range for this role is $121,280 - $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

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