Associate Staff CAD Engineer - Physical Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

 
Associate Staff CAD Engineer - Physical Verification 

Austin, TX 
 

Meet the Team 

As part of the Central CAD group, the CAD Physical Verification (PV) team develops and supports Physical Verification decks, including DRC, antenna, dummy fill, LVS, and extraction. The team collaborates with internal stakeholders to collect specifications and develop decks such as PERC, float, density, and XOR from scratch. In addition, the team develops and automates flows and methodologies to improve quality, performance, and the user debug experience. The team also collaborates with vendors to debug and resolve tool issues and to evaluate new features and tools 
 

Responsibilities 

• Development of various physical verification rule decks like DRC, LVS and dummy fill 

• Conduct and drive impact analysis meetings with stakeholders for deck releases 

• Collaborate with CAD, ESD, design, layout and foundry teams to obtain specifications for deck development. 

• Support design and layout teams to resolve any PV related issues during design development cycle  

• Conduct code reviews and create custom QA testcases to validate the quality of rule decks.  

• Develop and maintain PV flows and methodologies to improve quality and performance 

• Perform new tool/feature evaluations and benchmarks. 

• Work closely with external vendors to report and track bugs in the software 
   

Skills You Will Need 

• 10+ years of related professional experience with a bachelor’s or master’s degree in electrical engineering 

• Strong expertise in developing and supporting DRC, antenna, density and dummy fill rule decks using Calibre SVRF or similar languages 

• Experience coding LVS, extraction and PERC rule decks is a plus 

• Proven ability to independently drive new physical verification flows and methodologies from specification through release and adoption 

• Demonstrated experience working closely with design and layout engineers to debug and resolve issues during development lifecycle 

• Working knowledge of physical verification tools such as Calibre RVE, Calibre DRV, and virtuoso layout editor 

• Proficiency in scripting languages including