Senior Design Verification Engineer, HBM Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

For 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

High Bandwidth Memory (HBM) is a specialized computer memory interface designed for 3D-stacked synchronous dynamic random-access memory (SDRAM). HBM stacks multiple DRAM chips vertically, resulting in a compact form factor. It provides very wide data channels both within the stack and between the memory and processor. It can deliver high bandwidths needed for cutting edge applications like ML (Machine Learning) and AI (Artificial Intelligence). HBM incorporates RTL style logic design, custom high speed PHY design, analog circuit design, DFT circuits to deliver advanced HBM products using in-house and external foundry processes.

We are looking for a HBM Design Verification Engineer. Are you passionate about generating complex verification vector for next generation of HBM memory that will power leading edge AI applications? As a HBM Design Verification Engineer you will work in an innovative and dynamic team and will be responsible for developing verification plan, coverage, running simulations & debugging them for the HBM Interface die. In this position, you will collaborate with Micron’s world-wide design and verification teams and support the efforts of multi-functional teams such as Product Engineering, Central Verification teams, Methodology teams in developing simulation coverage and verifying HBM products to assure the best performance, functionality, quality, reliability, time-to-market, and customer satisfaction.

*This position will be a hybrid role located in either Atlanta, GA – Folsom, CA – Allen, TX

*The seniority level offered will be based on a combination of experience and education.

Responsibilities:

• Develop and execute comprehensive verification plans for HBM Interface die.

• Design and implement testbenches and verification environments using industry-standard tools and methodologies.

• Perform functional, regression, and performance testing to ensure designs meet specifications and quality standards.

• Collaborate closely with design engineers to identify and resolve design issues and discrepancies.

• Analyze and debug simulation results, providing detailed reports and recommendations for improvements.

• Maintain and update verification documentation, including test plans, test cases, and verification reports.

Qualifications & Skills:

• Experience with defining block, sub-system and full-chip top level test plans.

• Previous work experience in ASIC or Memory verification

• Deep understanding and knowledge of verification methodologies flows and quality metrics.

• Great debugging and problem-solving skills.

• Experience in AMS, High speed SerDes, PHY verification and co-sim

• Experience with memory controller, UCIe, PCIe/CXL IP/sub-systems.

• Experience in SystemVerilog, PLI coding

• Experience in UVM Test Bench

• Good understanding of CMOS circuit design

• Excellent problem-solving and analytical skills

• A self-motivated, phenomenal teammate who enjoys working with others

• Good communication skills with the ability to convey complex technical concepts with peers in verbal and written for