Performance Engineer

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Performance Engineer, you will work as part of a System IP team working on significant deliverables for the team. This is a mid to senior level position where the candidate will be in an individual contributor role, tasked with performance verification of mobile memory subsystem designs, correlation of RTL with performance model and performance modeling in C++ of memory subsystem, including interconnect, last-level cache, coherency, and memory controller. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

• You work on analyzing and verifying performance of system IP including system interconnect, memory controllers and cache subsystems.
• You understand and create infrastructure to run performance verification tests on memory-subsystem RTL.
• You analyze performance verification test results, interact with RTL team, generate waveforms, and propose environment as well as configuration changes.
• You understand and create infrastructure to run correlation patterns on RTL and performance model.
• You analyze correlation results in both RTL and C++, interact with relevant team to drive fixes into either model.
• You write performance models for the memory subsystem, including correlation fixes and new functionality.

Skills and Qualifications

Minimum Requirements:

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
• Experienced professional with understanding of the modeling and design process
• Works on problems of diverse scope where analyzing data requires evaluating identifiable factors
• Experience with industry standard RTL design tools and methodologies
• Solid experience in C++, ideally related to performance modeling

Preferred Qualifications:

• Performance verification of mobile memory subsystem design experience
• Experience with correlation of RTL with performance model
• Performance modeling in C++ of memory subsystem, including interconnect, last-level cache, coherency, and memory controller

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Mandatory Hybrid Work Requirement

Must be able to work in the office 3 days per week, with flexibility to work remotely on the remaining days. Employees are expected to adhere to the hybrid work sched