Senior Hardware Engineer, FPGA Design, Quantum

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
  
• 4 years of experience in Field-programmable Gate Array (FPGA) design and development.
  
• Experience with Register-Transfer Level (RTL) design using Verilog or systemVerilog.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
  
• Experience with Digital-to-Analog converters (DACs), Analog-to-Digital converters (ADCs), and high-speed communication protocols like Ethernet and PCIe.
  
• Experience with programming languages like C, C++, Python, or scripting languages like TCL.
  
• Experience in FPGA design and verification tools such as Quartus, Vivado, and industry-standard simulation and debugging software.
  
• Ability to Lead FPGA projects or ASIC block development from initial concept to final implementation.
  
• Ability to troubleshoot and resolve intricate design issues in FPGA systems within deployed environments.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

The US base salary range for this full-time position is $142,000-$211,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Collaborate with quantum physicists and hardware engineers to design and implement Field-programmable Gate Array (FPGA) architectures that will be used in the next generation of quantum systems.
  
• Develop and optimize the underlying Register-Transfer Level (RTL) code that powers FPGAs, ensuring they meet the unique demands of quantum computing.
  
• Test and validate FPGA designs, ensuring they are free of errors and perform as expected in both simulations and real-world quantum computing environments.
  
• Analyze and improve the performance, speed, and energy efficiency of FPGA designs.
  
• Communicate progress and findings to both technical and non-technical team members.