Sr. Staff Engineer - Digital Design Verification

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Company Overview</strong></span></p> <p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p> <p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p> <p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p> <p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p> <p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p> <p>If that's you, join us — the intelligence everywhere revolution starts here.</p> <p>&nbsp;</p></div><div class="pcty-row-flex pcty-margin-compact-all pcty-compact-margin-all css-0"> <div class="pcty-col css-a3cc3r"> <div class="" data-automation-id="job-description"> <h3>Responsibilities</h3> <p>You will be responsible for <strong>verifying complex digital designs</strong>, including Systems-on-Chip (SoCs) with multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic supporting IoT and edge-compute applications.</p> <p>The ideal candidate is a <strong>self-starter who takes full ownership of verification efforts</strong> and consistently delivers high‑quality, production‑ready silicon.</p> <p>Key responsibilities include:</p> <ul> <li>Own and execute <strong>end-to-end digital verification</strong> at block, sub-system, and full-chip (SoC) levels</li> <li>Develop detailed <strong>verification plans</strong> aligned with architecture and design specifications</li> <li>Perform <strong>SoC-level verification</strong> using full-chip simulation and regression environments</li> <li>Architect and implement <strong>scalable, reusable UVM-based testbenches</strong> using SystemVerilog</li> <li>Develop comprehensive <strong>test scenarios, stimulus, monitors, and checkers</strong> to achieve robust functional cov