Senior Staff Engineer, Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Custom Silicon Engineering (CSE) group is part of Data Center Engineering (DCE) Business Unit, closely collaborates with strategic Hyper scalar and Data Center customers in the development of advanced and highly complex custom SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.

What You Can Expect

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• Work on verification of memory subsystems of Marvell's AI/ML, Network processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs.
• Develop the verification components for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
• Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete.
• Debug failures and work with designers to resolve issues.
• Works independently and exercises judgement to make technical choices for obtaining results.
• Provide technical guidance to junior engineers

What We're Looking For

• Bachelor’s degree in Electrical engineering, Electronics, Computer engineering, or related fields with 5+ years of experience. Master’s degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 3+ years of experience.
• 5+ years of experience in design engineering with focus on verification.
• At least 3 years of direct hands-on verification experience on NOC, DDR and HBM memory subsystem at block, subsystem and full chip level contexts.
• Strong experience developing complex/random verification environments using System Verilog/UVM
• Strong experience with writing and executing detailed verification test-plan.
• Strong experience with scripting languages such as Python or Perl.
• Strong experience with object-oriented design and implementation.
• Excellent communication skills to interface internally and externally with all levels of the organization.
• Demonstrates good analytical and problem-solving skills.
• Must have the ability to multi-task in a fast-paced environment.

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws a