Lead Design Verification (DV) Engineer

About usWe are searching for talented individuals who are driven to tackle the most ambitious goal of our time - building the computer hardware that enables the development of safe artificial general intelligence. See more at fathomradiant.co/aboutus
In our people, we above all value kindness, a scout mindset, a focus on improvement, and prioritising to get the right things done. We aim to help build one of the most transformative technologies in the world, with massive social and ethical implications. We think this makes representation even more important, and we are actively striving to have a range of diverse perspectives on our team.
This role is open to remote from anywhere in the world.
We are looking for a design verification lead with a strong background in ASIC verification an interest in communication networks. You will work closely with other engineer teams to drive all aspects of the verification effort for our custom chip. Your primary scope of ownership will include verification planning, verification environment development, as well as leading both block-level and chip level functional verification effort for Fathom’s ASIC designs.

Areas of contribution:

• Develop and maintain comprehensive verification plans that covers all aspects of the design verification to ensure design correctness
• Lead the development and implementation of verification environments, testbenches, and test cases using industry-standard verification methodologies, tools, and frameworks
• Work closely with the design team to understand and validate the design requirements and specifications and to debug and resolve any issues that arise during the verification process
• Mentor and train junior DV engineers on best practices and industry standards

Requirements (necessary skills for the role):

• 5+ years of industry experience in ASIC design verification
• Demonstrable previous experience leading chip-level test plan and strategy development and environment setup
• Expert level knowledge of SystemVerilog, industry standard simulation tools and environments, including UVM
• Strong problem-solving and debugging skills
• Excellent communication and collaboration skills

Nice-to-haves (we will prioritize candidates that also have these skills):

• Knowledge of analog and mixed-signal (AMS) verification techniques and tools
• Experience with verification of high-speed interfaces such as PCIe, Ethernet, and SerDes
• Experience with emulation platforms

Indicative salary range for this role is $100,000 - $180,000. The range for this role is rather wide given that the salary will depend on the location and the experience level of the candidate.
For all roles, we target market salaries, with an additional benefits package. Our comprehensive benefits include startup equity, medical expenses coverage (including extra coverage for employees with a family).