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Senior DFT Engineer

Intel
United Statesfull_timeVerifiedPosted 31 Mar 2025
💰 $197,230/yr($139,710/yr$197,230/yr)

About the role

Job Details:

Job Description: 

Do Something Wonderful!Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Are you passionate about computer graphics and disrupting the industry with your innovation and working with leading Engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve Best-In-Class visual experiences that enable users to immerse themselves in a new visual future? Then our GPU Hardware IP (GHI) team has opportunities for you. Our Hardware development team designs and validates the future of Graphics engines. We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for one or more of the following activities: 
  • You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller
  • You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for.
  • Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.
  • Participates in the definition of architecture and microarchitecture features of the block being designed.
  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  • Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  • Supports SoC customers to ensure high-quality integration of the GPU block.
 The ideal candidate will exhibit the following traits/skills:
  • Excellent written and verbal communication skills
  • Demonstrate Leadership ability in driving execution
  • Demonstrate teamwork, problem solving and influencing skills
  • Ability to work with different geographical locations

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications:
  • Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 5+ years of industry experience
  • OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience
  • OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 2+ years of industry experience
  • Your experience should be in following
    • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.)
    • SoC or IP DFT design, integration or verification
    • EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools.
 Preferred Qualifications:
  • Silicon enabling debug or test pattern development experience
  • Design automation skills and proficiency in programming or scripting languages
  • Structural design flows, including timing, routing, placement or clocking analysis
  • High volume manufacturing requirements and test flows
  • 3D, media and display graphics pipelines
  • SoC architecture

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

US, Arizona, Phoenix, US, Ca

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Company

Intel

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