Senior DFT Engineer

<h2>Senior DFT Engineer</h2> <h2> </h2> <h2>About the job</h2> <p>Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is a multi-disciplinary field of growing complexity which involves cooperation among multiple VLSI engineering skills, including de</p> <p>We offer you:</p> <p>· Competitive Salary &amp; Benefits;</p> <p>· Respect for your private life and your choices;</p> <p>· All tools required for high performance in your field;</p> <p>· Responsible approach, long-term commitments and stability</p> <p>sign, architecture, verification, backend, timing, test, ATE and reliability and more.</p> <p>Take the opportunity and join us as a Senior DFT Engineer!</p> <p> </p> <h2>Qualifications</h2> <p>Desired qualifications/skills:</p> <ul> <li>6+ (desirable) years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs;</li> <li>Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST;</li> <li>Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite;</li> <li>Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus;</li> <li>Hands-on in Perl/Tcl/Python scripting;</li> <li>Excellent analytical, and problem-solving skills</li> </ul> <h2>Job Responsibilities</h2> <p>Your role:</p> <p>· DfT implementation inline with existing test methodology for advance process nodes;</p> <p>· Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST;</p> <p>· Closely work with physical design team to resolve timing constraints/issues;</p> <p>· Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues;</p> <p>· Debug and improve important DfT KPIs: test coverage/pattern efficiency;</p> <p>· Hierarchical retargeting;</p> <p>· Silicon bring-up, diagnosis and support for physical failure analysis</p> <p>#LI-AP17</p>