Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

 We are looking for a Senior Physical Design Engineer with power analysis/optimization expertise to join the team.

#SCHIE #CSME

The candidate for this position will be expected and able to complete the following responsibilities:

• Responsible for SOC low power design methodology and power signoff.
• Drive methodology exploration activities to optimize SOC blocks for power, performance, and area (PPA).
• Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
• Responsible for RTL to GDS implementation in Physical Design domain.
• Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
• Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.
• Demonstrate technical expertise across various domains of Physical Design.
• Clear communications on project status & planning.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience.

Preferred Qualifications:

• 7+ years of experience in semiconductor design.
• Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
• Production silicon tape-outs experience in advanced foundry process nodes.
• Experience in low power design methodology for SOC
• Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
• Familiarity with industry-standard power analysis EDA tools (such as PrimePower)
• Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal