Principal Engineer, SOC IP Systems & Lifecycle Management

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><h3><strong>Role Objective</strong></h3> <p>As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won't just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our "AI-first" IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally "SOC-ready," preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach.</p> <p>The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful candidate will have the right expertise to run all EDA tools, understand the results, challenge the false pass scenarios, and dig into the root cause of real errors. They will work with the vendors or with our internal IP teams to solve the issues.</p> <p>They will be responsible for ensuring that all IP deliveries are integrable, timing-clean, and manufacturable, preventing "late-stage" SOC breaks caused by inconsistent IP views or structural violations. IPQA will cover all aspects of the design flow starting from Architecture coherence, PPA evaluation, Front-End integration, SDC, RDC, D