Staff Engineer, SoC RTL Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design.<br><br>This role is hybrid, based out of Tokyo.</p> <p><br>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>A digital design expert with a deep understanding of computer architecture and IP microarchitecture.</li> <li>Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.</li> <li>Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.</li> <li>A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.</li> <li>Strong synthesis and timing closure awareness to support backend teams.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.</li> <li>Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.</li> <li>Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.</li> <li>Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.</li> <li>Prior experience in on-chip fabric and interconnect designs and basic understanding of RISC-V Architecture and debug experience is preferable.</li> </ul> <p> </p> <p><strong>What You Will Learn</strong></p> <ul> <li>How cutting-edge chiplet design are built, from spec to silicon.</li> <li>What it takes to collaborate with teams designing novel proces