Principal Engineer, Physical Design

<div class="content-intro"><p><strong>About InnoPhase IoT</strong></p> <p>If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT.</p> <p>We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!</p></div><p><strong><u>Overview of Role</u></strong></p> <p>As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA,&nbsp;PV/EMIR/Noise/SigEM cleanup and signoff&nbsp;on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.</p> <p>&nbsp;</p> <p><strong><u>Location</u></strong></p> <ul> <li>San Diego or San Jose, CA</li> </ul> <p>&nbsp;</p> <p><strong><u>Responsibilities</u></strong></p> <ul> <li>Complete entire physical implementation of the block and chip level</li> <li>Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&amp;route, timing noise, physical verification, IR/RV.</li> <li>Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs</li> <li>Analyze the quality of the floorplan and Customized&nbsp;Clock tree structure and Place &amp; Route</li> <li>Implement ECOs for timing closure</li> <li>Signal EM/Noise and Power&nbsp;IR/EM analysis and fix</li> <li>DRC/LVS/ERC/ANTENNA analysis and clean up</li> <li>Timing verification and signoff</li> <li>Physical verification and sign off</li> </ul> <p>&nbsp;</p> <p><strong><u>Minimum Qualifications</u></strong></p> <ul> <li>Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience</li> <li>Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.</li> <li>The entire SOC implementation an