Engineering Program Manager, RISCV

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>We’re looking for a driven Engineering Program Manager—or a hands-on technical lead ready to step into program management—to help lead the charge on our RISC-V CPU team. In this role, you’ll be at the center of the action, working across architecture, design, verification, physical design, and DFT to drive the full lifecycle of a high-performance CPU—from spec to tapeout to post-silicon debug. You’ll partner with key stakeholders to define bold objectives, lock in milestones, and align the resources needed to bring next-gen compute to life.</p> <p>This role is hybrid, based out of Austin, TX or Santa Clara, CA.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>A technically strong leader with experience in CPU, SoC, or silicon development.</li> <li>Skilled in aligning cross-functional teams to deliver complex, high-performance hardware programs.</li> <li>Proactive problem solver who thrives in dynamic, fast-paced environments.</li> <li>A clear communicator who can engage engineers and executives alike.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Ownership of full-cycle CPU program management—from spec to tapeout and post-silicon debug.</li> <li>Ability to define scope, schedule, and resources, and lead execution across architecture, design, verification, and DFT teams.</li> <li>Proven experience driving silicon development, managing risk, and delivering milestones.</li> <li>Experience with Functional Safety (FuSa) standards and implementation, especially ISO 26262 and an understanding of automotive industry requirements and standards for hardware development is highly desirable.</li> </ul> <p> </p> <p><strong>What You Will Learn</strong></p> <ul> <li>How to lead the delivery of cutting-