HW SOC/ASIC Physical Design Engineer, Senior (US Citizenship Required)

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.

** Must be a U.S. citizen and eligible to receive a U.S. Government security clearance **

We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR), DRC and Timing closure. This role involves architecting and implementing robust, low-skew, power-efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals.

This role requires full-time onsite work in San Diego, CA (5 days per week).

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Key Responsibilities:

• Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2).

• Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime).

• Collaborate with RTL designers to resolve timing, congestion, and DRC issues.

• Optimize design for power, performance, and area (PPA).

• Conduct formal equivalence checks between RTL and netlist.

• Support physical verification including DRC, LVS, and antenna checks.

• Work closely with backend teams for tapeout preparation and signoff.

• Excellent scripting skills (TCL, Python, Perl) for reference flow automation.

• Execute full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry-standard tools (e.g., Calibre, Pegasus, ICV).

• Customize and optimize reference physical verification flows to align with project needs and foundry requirements.

• Perform GDS-to-GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness.

• Debug and resolve physical verification violations, working closely with layout, design, and CAD teams.

• Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists.

• Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.

• Develop and maintain automation scripts for verification flows, reporting, and regression testing.

• Interface with EDA vendors to resolve tool issues and improve flow robustness.

• Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability.

• Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.

• Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).

• Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners.

• Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices.

• Debug and resolve setup, hold, and transition violations across various PVT corners.

• Drive timing closure through iterative optimization and ECO implementation.

• Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability.

• Analyze clock tree timing, including skew, latency, and jitter impacts.

• Support signoff timing verification, including cross-domain timing and false/multicycle path handling.

• Interface with EDA vendors to resolve tool issues and improve flow robustness.

• Participate in design reviews, providing insights on timing risks and mitigation strategies.

• Define and implement low-power architecture using CLP methodology across RTL and physical design stages.

• Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications.

• Customize and