Sr. Staff Engineer - Timing Methodology

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Company Overview</strong></span></p> <p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p> <p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p> <p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p> <p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p> <p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p> <p>If that's you, join us — the intelligence everywhere revolution starts here.</p> <p>&nbsp;</p></div><p><strong><span data-contrast="none">Scope</span></strong><span data-contrast="none"> </span><span data-ccp-props="{&quot;134233117&quot;:true,&quot;134233118&quot;:true,&quot;201341983&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></p> <div class="pcty-row-flex pcty-margin-compact-all pcty-compact-margin-all css-0"> <div class="pcty-col css-a3cc3r"> <div class="" data-automation-id="job-description"> <p>As a Sr. Staff Engineer - Timing Methodology, you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well.</p> <strong>Responsibilities:</strong> <ul> <li>In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.</li> <li>Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power.&