Job Details:

Job Description: 

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply.

This job opportunity in IFS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to IFS customers, differentiating and accelerating their solutions from architecture to post-silicon validation.

As a Structural (Physical) Design Engineer Design your responsibilities include:

• Developing and supporting digital circuit design with cell libraries. Performing digital circuit design and simulation.
• Designing, developing, modifying, and evaluating digital electronic parts, components or integrated circuitry for use in digital electronic equipment and other hardware systems.
• Determines design approaches and parameters. Performs digital circuit design, verification and layout, data path design and digital block synthesis, place and route, sign-off through tape-out.

The Structural (Physical) Design Engineer will exhibit behavioral traits that demonstrate Excellent verbal and written communication and collaboration skills.

Strong communication and collaboration skills, including a willingness to work with others, and the ability to tolerate ambiguity and highly complex decision environments.

Qualifications:

What we need to see (Minimum Qualifications):
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

The candidate must have a Bachelor's degree in Computer/Electrical Engineering or Computer Science and 8+ years of experience -OR- a Master's Degree in Computer/Electrical Engineering or Computer Science and 6+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science and 3+ year of experience with the following:

• Experience with owning the full chip level and taping out multiple complex SoCs
• Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.
• Hands on experience with Full-Chip and partition level physical design (APR digital logic).
• RTL to gds2 flow and basic device physics.
• Scripting with tcl, perl, shell etc. to solve the basic design problem.
• Internal flow development and understand nuances of Physical Design (Structural Design) flow.
• Experience with 7nm technology or below.

How to Stand out (Preferred Qualifications):

• Experience with handling PDKs (Process Design Kit).
• Strong Experience with Floorplanning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floorplanning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, design sign-off tools like and