Sr. Memory Controller Micro-Architect (Principal Engineer)

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Sr. Memory Controller Micro-Architect, you will lead the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

In this high-impact role, you will have ownership and influence entire memory-controller related micro-architecture, RTL design, and performance/power optimization. As part of a true global task force, you will collaborate closely with system architects, verification, performance/power, design implementation, and other teams to transform bold ideas into next-generation memory technologies for Samsung. You are empowered to deepen your expertise in memory controller by being at the forefront of a full technology development cycle and redefining what’s possible.

• You are a domain expert in one or more technical areas with solid engineer foundation and RTL design experience. You will drive the micro-architecture, RTL design, debug, and timing closure for custom memory controllers.
• You are passionate about handling microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and delivering high quality RTL on schedule to meet performance, power, an area (PPA) goals.
• You ensure design quality through LINT, CDC, ECO flows, and power analysis (PowerArtist).
• You have a collaborative mindset and build strong cross-functional partnerships with various stakeholders to ensure design functionality, achieve PPA goals, and resolve implementation challenges with evolving priorities in a fast-paced environment.
• You take ownership in your deliverables by adhering to JEDEC standards and timing parameters, collaborating with SOC IP delivery with all sanity checks, supporting timing debug and closure, and applying knowledge of DDR PHY.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier