SOC Engineering, Physical Design Architect- 13350

General Information

Job Title SOC Engineering, Physical Design Architect- 13350 Job ID 13350 City Sunnyvale State/Province California Date Posted 07-Nov-2025 Job Category Engineering Job Subcategory SOC Engineering Hire Type Employee Remote Eligible No Base Salary Range: $209000 - $313000

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced IC physical design expert, with strong leadership in digital implementation and signoff for complex, high-speed mixed-signal subsystems. You thrive in collaborative environments, can manage both local and remote teams, and have a proven track record of driving projects to tapeout. You’re hands-on, detail-oriented, and passionate about optimizing performance, power, and area. Your communication skills and technical insight make you a go-to resource for cross-functional teams.

What You’ll Be Doing:

• Lead and manage physical design teams for high-speed subsystem implementations.
• Guide timing constraints and signoff for designs with hundreds of clocks.
• Drive PNR flow for deep sub-micron, multi-million gate designs.
• Execute synthesis, floorplanning, partitioning, DFT, low power/UPF, and signoff tasks.
• Collaborate with front-end, analog, and program management teams.
• Provide feedback for architectural and timing improvements.

The Impact You Will Have:

• Deliver signoff-quality, high-performance silicon solutions.
• Mentor and develop engineering teams.
• Drive process improvements and technical innovation.
• Enhance Synopsys’ leadership in high-speed IP.
• Facilitate successful cross-team collaboration.
• Enable next-generation chip architectures.

What You’ll Need:

• MS in Electrical Engineering; 10+