Principal Design Engineer, NVEG

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Department intro:

The Non-Volatile Engineering Group (NVEG) at Micron contributes to the development of memory products that are best-in-class in terms of die size, performance, reliability, and power.  Our NVEG organization is dedicated to advancing non-volatile memory technologies such as NAND. Our primary mission is to innovate and develop groundbreaking solutions that improve the performance and reliability of non-volatile memory products.

Role overview:

The Principal Design Engineer in Micron’s NVEG organization contributes to the development of new memory products by assisting with the overall design, layout, and optimization of datapath circuits for NAND flash memory. This position will drive task forces and make strategic decisions on major datapath architectural changes influenced by new design specs such as higher speed/lower power. They will assess pros and cons of new architecture and drive all activities pertaining its implementation. The role will be expected to lead technical datapath design projects, directing the design planning, layout, and validation activities according to project timelines.

Responsibilities:

• Manage major block design (IO top, pad top, tile dp) placement, floor-planning, and architecture based on project timing, area, and power requirements. Drive major block validation activities.

• Perform block level HSPICE, full chip level timing, or functional validation of any mode/function of datapath

• Lead full chip XA environment setup

• Communicate with project teams and other functional teams on design and specifications of major block interfaces

• Evaluate post-silicon timing issues, marginality issues, and yield drop through root-cause analysis

• Communicate with PE to drive silicon experiments and propose fixes and improvements. Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations.

• Communicate with device modeling and CMOS process teams on CMOS device model and device characteristic change requests based on design requirements

• Collaborate with ASIC, MNAND, SSD, and Signal Integrity teams to understand different NAND ecosystem environments, limitations, and usage cases, incorporating this understanding into NAND IO design

Minimum qualifications:

• BS or MS in Electrical Engineering with 8+ years of relevant experience

• Advanced knowledge and understanding of high-speed IO circuit performance, power and area optimization, and chip architecture/floorplan

• Experience with managing complex design projects, effectively communicating progress and outcomes

• Demonstrated experience with device characterization and modeling techniques

• Advanced use of yield enhancement, root-cause analysis, and FMEA principles

• Experience in physical design flows and optimization

Preferred qualifications:

• PHD with 5+ years of relevant semiconductor industry experience

• Experience with EDA tools (cadence, HSPICE, XA, Verilog), plus Python and Matlab for design flow automation

• PMP or Lean Six Sigma certification

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$140,000.00 - $298,000.00 a year

Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. 

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

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