Senior Digital Design Engineer (AI Fabric)

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong>Overview</strong><br>Join our team as <strong>Senior Digital Design Engineer</strong> to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Own the RTL implementation of complex digital designs from micro-architecture through sign-off.</li> <li>Collaborate with verification teams to review test plans and debug issues.</li> <li>Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.</li> <li>Scripting and automation for ASIC methodology improvement.</li> <li>Accountable for quality and overall design success with the support of senior engineers.</li> </ul> <p><strong>Required Qualifications</strong><br><strong>Education &amp; Experience:</strong></p> <ul> <li>Bachelor’s degree in electrical engineering or equivalent</li> <li>3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets</li> </ul> <p><strong>Digital Design Expertise:</strong></p> <ul> <li>Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.</li> <li>Track record of delivering h