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Senior Design Verification Engineer

Capgemini
Braşov, Romaniafull_timeVerifiedPosted 24 Nov 2023

About the role

About the job

Is design verification your passion? Do you see yourself growing exponentially in this remarkable field by bringing your valuable contribution to the world in the long run? Are you a highly motivated Senior Design Verification Engineer with more than 6 years of work experience, you have hands-on experience in SystemVerilog, Verilog, or VHDL, with good experience in Constrained Random and Coverage Driven Verification with UVM/OVM?

Then, I invite you to take a quick view at the job requirements below. If you are interested you can apply directly, ping me in a LinkedIn message, or send me your CV at maria.a.constantinescu@capgemini.com . If you have questions, feel free to drop me your inquiries, and I will do my best to answer you.

Take the opportunity and join us as a Senior Design Verification (DV) Engineer.

You can share the role further with peers from your communities, give a like, or leave a comment with the details of the person who might be interested.

Your role - what we value from you

  • Own verification of IP’s and SoC’s in prototype and SoC design environment;
  • Establish functional and performance benchmarks;
  • Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
  • IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IPs/SoCs.

You are equipped with

  • Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM
  • Experience in creating any UVC components or sequences is a must
  • Basic knowledge of at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification, etc. Expertise in one protocol is a must for seniors and above.
  • Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus)
  • EDA simulation/debugging tools agnostic;
  • Good knowledge of Perl/TCL/Python scripting;
  • Domain expertise on any one of these for senior and above CPU processor/server, multimedia, automotive, Ethernet, Mobile;
  • Great communication skills;
  • You are proficient in English (B2-C1 level).

 

Nice to have (not mandatory):

  • SystemC proficiency

 

What you can expect from us

 

  • Competitive Salary & Benefits;
  • Knowledge and support from more experienced engineers;
  • All tools required for high performance in your field;
  • Long-term commitments, and stability;
  • Flexible working hours and hybrid work (remote office);
  • Specialization - and further development opportunities.

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Company

Capgemini

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