Design Verification Intern -RISCV CPU

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>In this role, you will learn Functional verification of high-performance CPUs going into industry leading AI/ML architecture. You will be mentored by and work alongside a group of highly experienced engineers across various domains of the AI chip.</p> <p>This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.</p> <p><span style="text-decoration: underline;"><strong>This is for our Fall 2026 Semester</strong></span></p> <div><strong>Who You Are</strong></div> <div> <ul> <li>Passionate about computer architecture and curious about how cutting-edge CPUs actually work.</li> <li>Enrolled in a BS, MS, or PhD program in EE, CE, CS, or a related field, with a strong academic record.</li> <li>Experienced with C++, SystemVerilog, or scripting languages through coursework or personal projects.</li> <li>Comfortable thinking at both the software and hardware level—including assembly and RTL.</li> </ul> </div> <div><br><strong>What We Need</strong></div> <div> <ul> <li>Contribute to the functional verification of high-performance CPUs designed for general purpose and AI/ML applications.</li> <li>Help develop DV test plans and testbenches for both ISA and microarchitecture-level features.</li> <li>Debug RTL code and assist in making real design changes that impact chip development.</li> <li>Build tools and write stimulus code that can scale across pre-silicon to post-silicon environments.</li> </ul> </div> <div><br><strong>What You Will Learn</strong></div> <div> <ul> <li>Get hands-on experience verifying state-of-the-art AI/ML hardware with guidance from experienced engineers.</li> <li>Explore how performance, RTL, and DV tools come together in a full-chip environment.</li> <li>Deepen your understanding of CPU design, ISA-level verification, and system-level debugging.</li> <li>Work in a real-world engineering team and gain exposure to industry-standard workflows and toolchains.</li> </ul>