Principal Physical Design Engineer
MarvellAbout the role
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, and networking applications.
What You Can Expect
As a senior technical contributor in the central physical design team, you will:
Drive improvements in physical design methodologies, flows, and automation to enhance productivity, PPA, and signoff quality
Own RTL‑to‑GDSII implementation for complex blocks or partitions, including synthesis, floorplanning, PnR, CTS, timing closure, IR/EM/crosstalk analysis, and physical verification (DRC/LVS)
Solve complex technical challenges across congestion, timing, signal‑integrity, and design‑rule issues, partnering closely with RTL, STA, and verification teams
Collaborate cross‑functionally to influence design decisions, constraints, and micro‑architecture choices that improve physical feasibility
Guide and mentor junior engineers, sharing best practices and helping elevate engineering capability across the organization
Contribute to next‑generation design methodologies and help evaluate new tools, technologies, and automation opportunities
Work closely with global timing and architecture teams to debug and resolve block‑level and subsystem‑level timing issues
Engage with EDA vendors to drive tool enhancements and participate in evaluations of new features or flows
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree.
Proven ability to drive physical design execution for large, high‑performance chips and contribute to successful, high‑quality tape outs under aggressive schedules
Deep expertise in hierarchical physical design strategies, advanced-node implementation challenges, and industry‑standard methodologies
In‑depth understanding of current foundry technologies and design constraints
Strong understanding of the ASIC design flow, including RTL integration, synthesis, PnR, timing closure, and signoff
Expert-level knowledge of modern EDA tools and flows across implementation, analysis, and verification
Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to improve flow robustness and efficiency
Strong communication and collaboration skills, with the ability to influence and work effectively across cross‑functional engineering teams
Experience contributing to the development and deployment of advanced physical design methodologies and flows
Strong knowledge of static timing analysis (PrimeTime, Tempus), EM/IR‑drop and crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction tools (Quantus, StarRC), and formal/physical verification tools (Formality, Verplex, Calibre, Hercules). (Experience with all tool
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