Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. 

The Azure Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance chip with the capability to efficiently handle large data volumes. Thanks to its integrated design, this solution empowers Azure to develop solutions for solving the next generation problems with increased agility and performance leveraging the DPU’s compute, storage, and networking capabilities. 

We are seeking a Senior Physical Design Engineer. As part of our DPU silicon team in Santa Clara, you will help lead the way for our cutting-edge ASICs, supporting our world-class silicon Physical Design team. In this role, you will tackle key design challenges and support the team with your expertise in design flows, automation, and as an interface to our CAD vendors and support teams. You will bring your experience in end-to-end RTL to GDS flows to help drive efficient, on-time execution of our tapeouts.

Responsibilities

• Take full ownership of key deigns and deliver for tapeout, meeting all timing, physical, electrical, and manufacturing requirements
• Ownership of flows and automation for key physical design tools (place & route, extraction/STA, physical verification, etc); deploy and test new flows; debug issues & improve existing flows
• Work closely with PD and FE team members across functions and geographies to monitor, track, and resolve issues in our tools and design flows
• Work with tool vendors to resolve key design challenges, improve our flows, and resolve tool issues
• Work closely with PD team members to drive quality and QOR improvements

Qualifications

Required qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 4+ years of physical design experience, with demonstrated experience in delivering tapeout-ready GDS
• 3+ years of experience supporting design flows for synthesis, place-and-route, and signoff
• 3+ years of experience Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime), including integration of in-design signoff flows such as ICV, PrimeClosure, or Redhawk

Other qualifications:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred qualifications:

• 10+ years of hands-on physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR closure)
• Deep understanding of Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime), including integration of in-design signoff flows such as ICV, PrimeClosure, or Redhawk
• Experience with flow automation
• Thorough understanding of STA & timing constraints
• Demonstrated tapeout experience in TSMC 5nm/3nm or below

Silicon Engineering IC4 - The typical base pay ra