Job Details:

Job Description:

Altera is seeking a highly experienced Senior Principal Engineer / Subject Matter Expert (SME) to drive the architecture, development, and advancement of next-generation timing analysis, modeling, and optimization technologies within the Quartus FPGA Compiler.

This role will provide technical leadership across the Quartus compilation flow, with a particular emphasis on Static Timing Analysis (STA), timing closure, timing modeling, optimization algorithms, and scalable compiler infrastructure. The successful candidate will work closely with architecture, synthesis, fitting, routing, and timing teams to improve compiler quality of results (QoR), runtime, scalability, and signoff correlation for next-generation FPGA devices.

The ideal candidate is recognized as an industry expert in timing analysis and optimization with deep experience building high-performance EDA engines and solving complex timing convergence challenges across large-scale digital designs.

Key Responsibilities

Quartus Timing Analysis & Optimization Leadership

• Define and drive the technical roadmap for timing analysis, timing modeling, and timing optimization within the Quartus FPGA Compiler.

• Lead the design and implementation of advanced timing engines supporting FPGA compilation, placement, routing, and timing closure.

• Develop methodologies to improve timing convergence across the Quartus RTL-to-bitstream flow.

• Partner with architecture and compiler teams to enable best-in-class timing QoR and signoff correlation.

Static Timing Analysis (STA)

• Architect and develop next-generation STA capabilities, including graph-based and path-based timing analysis.

• Advance support for complex timing scenarios, including:

  • Multi-corner, multi-mode (MCMM) analysis

  • Timing exception handling

  • Clock domain crossing analysis

  • Variation-aware timing methodologies

  • Incremental timing analysis

• Improve timing accuracy while maintaining industry-leading scalability and runtime performance.

Timing Modeling & Signoff Correlation

• Develop timing modeling methodologies that accurately correlate Quartus results with silicon behavior and signoff requirements.

• Drive innovations in delay modeling, clock modeling, timing abstraction, and hierarchical timing analysis.

• Partner with FPGA architecture teams to ensure accurate representation of device resources and timing characteristics.

Compiler Algorithms & Infrastructure

• Design scalable data structures and algorithms for timing analysis and optimization.

• Improve compiler performance through parallelization, multi-threading, and incremental processing techniques.

• Drive architectural improvements that enable efficient handling of large, complex FPGA designs.

Cross-Functional Technical Leadership

• Provide technical mentorship and thought leadership across engineering teams.

• Collaborate with synthesis, placement, routing, architecture, verification, and software engineering organizations.

• Influence future FPGA compiler capabilities through technical strategy, innovation, and long-term planning.

Qualifications:

Required Qualifications

• MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field.
   

• 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains.
   

• Deep expertise in:

  • Static Timing Ana