Senior Signal and Power Integrity Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
• 8 years of experience with signal and power integrity modeling and simulation for high-speed interfaces (e.g., LPDDR, MIPI, UFS, PCIe, USB).
• Experience with electromagnetic theory, transmission line concepts, and circuit design.
• Experience with EM simulation tools (e.g., HFSS, SiWave, PowerSI, Clarity) and circuit simulation tools (e.g., Hspice, Spectre, ADS).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
• 8 years of experience in the signal and power integrity field.
• Experience in Power Delivery Network (PDN) modeling, simulation, and correlation, including PMIC design concepts.
  
• Experience in Power Delivery Network (PDN) modeling, simulation, and correlation, including PMIC design concepts.
  
• Experience with lab equipment for validation and debugging (e.g., high-speed oscilloscope, TDR, VNA).
• Experience with on-chip power analysis flows (e.g., PTPX, Redhawk, Voltus).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Execute package design studies, including technology selection, stack-up optimization, and layout.
• Perform model extraction and simulation for system-level power and signal integrity across core power, Low Power Double Data Rate (LPDDR) memory, and high-speed I/O interfaces.
• Develop and refine signal and power integrity methodologies and generate system-level design guidelines.
• Conduct lab validation, perform correlation studies between simulation and measurement, and debug root-cause issues.
• Collaborate with cross-functional teams, including SoC design, package design, and system hardware to deliver optimized solutions.