Senior ASIC Designer

🚀 Join Our Team as a Senior ASIC Designer 🚀

About the Role

Vipas AB is seeking a Senior ASIC Designer for a leading technology client in Stockholm. You will work end-to-end with ASIC/SoC development, taking ownership from architecture and RTL design through tape-out, while collaborating closely with cross-functional teams.

Key Responsibilities & Skills

• Ownership of ASIC projects from specification to tape-out and bring-up

• Define and document chip-level and system architectures

• Expert RTL design using Verilog/SystemVerilog

• Strong understanding of microarchitecture, clocking, resets, power domains, FSMs, pipelining

• Collaboration on verification using SystemVerilog/UVM and simulators (VCS, Questa, ModelSim)

• Hands-on experience with synthesis, timing constraints, and timing closure

• Guide physical design teams on floorplanning and timing paths

• Knowledge of low-power design (UPF/CPF, clock gating, DVFS) and DFT concepts

• Modeling and system-level analysis using Python, C/C++, or SystemC

• Scripting and automation using Python, Perl, or Tcl

Nice to Have

• AI/ML accelerators, networking, or video processing experience

• Chiplet or 2.5D/3D packaging exposure

• Security, post-silicon validation, FPGA prototyping, or HW/SW co-design

Why Vipas AB?

At Vipas AB, we see our consultants as partners – not just resources.
We offer:

• Assignments aligned with your skills and professional development

• Close and personal dialogue throughout the assignment

• Transparency regarding assignment scope, expectations, and conditions

• Opportunities to work in technically advanced and innovative environments

• A company that values trust, responsibility, and long-term collaboration

Interested?

Submit your application or contact Vipas AB for more information.

Apply today:
Send your application to shrini@vipas.se or contact us at +46 728479197.