Job Details:

Job Description:

About the Company

Altera is one of the world's leading providers of programmable solutions. With a renewed focus on agility, software-first, and AI-driven solutions, Altera is shaping the future of computing by providing flexible technology, empowering innovators with scalable products, from high-performance to power- and cost-optimized devices for cloud, network, and edge applications. Join us in our journey to becoming the #1 FPGA provider in the world as we redefine the next era of programmable innovations!

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries. Join us in our journey to becoming the #1 FPGA company!

About the Role

As a Design Methodology TFM Lead you will have the opportunity to:

• Collaborates with EDA vendors on defining and early testing of next generation design tools.

• Participates in the development and improvement of physical design methodologies and flow automation.

• Possesses expertise in various aspects of physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Experience in both EDA tools (SNPS and CDNS) PnR flow is a must.

• Will contribute to enable Dual Flows for implementation.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142.6k - $206.5k USD

Qualifications:

What We Want to See  

12+ years of total experience, experience should include:

• In depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools.

• In depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow.

• Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog.

• Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Education Requirement

• BS degree in computer engineering, electronic Engineering, or related field (Master’s Preferred)

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.