Senior Technologist Engineer, VLSI Design Engineering

Company Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Job Description

The Memory Technology Group is at the core of the Legacy Sandisk Engineering Organization. We are building a cutting edge 3D memory in our multi-billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost without forgoing quality. The Memory Technology organization is a strategic entity for the company and we are constantly growing. Our group functions as a start-up and offers a creative, fast paced, entrepreneurial work environment where you’ll be at the center of innovation.

We are looking for an experienced Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and has a great track record for delivering innovative results.
You will need to think creatively about the memory as we do take pride in our craftsmanship.  We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.

Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative, and focused team!

In this position, the individual will be responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.

ESSENTIAL DUTIES AND RESPONSIBILITIES: 

• RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure
• Balance design trade-offs with modularity, scalability, power, area, and performance.
• Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
• Participating in Post-Si evaluation and debug
• Drive cross function support for productization
• Technical guidance and mentoring of junior engineers

Qualifications

REQUIRED:

• MSEE plus 15 years of relevant experience
• Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
• Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
• Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
• Excellent communication (written and verbal) and interpersonal skills

PREFERRED:

• Experience leading silicon design project.
• Experience developing digital circuit designs for low power operating conditions
• Working knowledge of device physics and process
• Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
• Proficiency with following Digital design tools
  • Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
  • Static Timing - Synopsys Primetime or Cadence Tempus
  • Place and Route - Synopsys ICC or Cadence Encounter or Innovus
• Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
• Programming experience in C, C++, Python or Perl

SKILLS: