Senior Digital Hardware Engineer — FPGA & Signal Integrity

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!  

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

As a Senior Digital Hardware Engineer at Blue Origin, you will design and develop FPGA-based hardware for our next-generation RF communication and beamforming systems. You will be a hands-on schematic and signal integrity engineer, owning board-level FPGA hardware design from component selection through schematic capture and SI analysis, and providing technical oversight of internal or third-party PCB layout engineers and fabrication partners.

Responsibilities:

• Design FPGA-based digital boards interfacing to beamforming ASIC carrier boards with high-speed control interfaces and precision clock distribution, digital interface and timing distribution boards connecting back-end processing to phased array antenna modules, and mixed-signal payload integration assemblies managing power, clocking, and inter-board data routing

• Create complete electrical schematics in Altium Designer for FPGA-based boards including I/O bank planning, power rail grouping, configuration circuitry, and JTAG/debug infrastructure

• Design multi-rail power distribution for FPGAs and ASICs including sequencing, point-of-load regulators, and power monitoring

• Select and evaluate components with consideration for performance, availability, and temperature range

• Define PCB stackup requirements in collaboration with fabrication partners, specifying laminate selection, copper weights, and layer assignments for impedance and loss targets

• Author routing constraint documents for high-speed interfaces (JESD204B/C, DDR4, LVDS) covering length matching, topology, spacing, termination, and reference plane rules

• Perform pre- and post-layout SI review using simulation tools (HyperLynx, SIwave, or equivalent) with particular attention to via stub effects, crosstalk, and connector transitions

• Review third-party layout deliverables against constraint documents and SI simulation results, providing clear and actionable feedback

• Support PDN analysis for FPGA and ASIC power rails

• Develop board bring-up procedures and test plans prior to first article fabrication

• Support hardware bring-up using oscilloscopes, logic analyzers, and BERT instruments to characterize high-speed interfaces

• Debug and document hardware issues, driving root cause analysis and design corrections

Minimum Qualifications:

• B.S. in Electrical Engineering or related field with 5+ years of board-level hardware design experience

• Hands-on schematic design experience with high-performance FPGAs (Xilinx UltraScale+, Intel Agilex, or equivalent)

• Working knowledge of signal integrity fundamentals: transmission lines, impedance control, via effects, and termination — sufficient to author layout constraints and review third-party layouts

• Experience designing and validating high-speed serial interfaces at 16 Gbps lane rates or higher, with direct ownership of schematic and SI analysis at that rate

• Experience with at least one high-speed serial interface standard (JESD204B/C, PCIe Gen4/5, or equivalent) including schematic ownership

• Proficiency in Altium Designer for multi-sheet schematic design

• Familiarity with SI simulation tools (HyperLynx, SIwave, or equivalent) at a layout review level

• Hands-on bring-up experience with oscilloscopes, logic analyzers, and standard lab equipment

Preferred Qualifications:

• Experience designing hardware for phased array or beamforming systems including phase array antenna module interfaces, array timing distribution, or beamforming ASIC integration

• Familiarity with JESD204B/C deterministic latency, SYSREF distribution, and multi-converter synchronization

• Familiarity or hands-on experience with Precision Time Protocol (