Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Physical Design Engineer to join the team.

Responsibilities

• Lead and manage floorplanning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).
• Drive end-to-end execution from synthesis through place-and-route for large sub-chips and/or full-chip designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Coordinate effectively across cross-functional teams such as DFT, RTL/Design/IP, STA, CAD, Architecture, Power & Performance, and both internal and external stakeholders.
• Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
• Develop and implement robust clock distribution strategies that meet design specifications.
• Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
• Provide technical leadership and foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.

Qualifications

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience.
• 4+ years experience in semiconductor design.
• 3+ years experience implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 

Preferred Qualifications:

• Experience in large-scale SoC, CPU, and IP design tape-outs using advanced foundry process nodes.
• Cabable communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proficient in power rollup methodologies with hands-on experience at both block and full-chip levels.
• Project management capabilities with a proven ability to manage multiple concurrent projects effectively.
• Expertise in constraints generation, static timing