Sr Staff Analog Layout Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Group Description
Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

This is a rare foundational engineering opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.

What You Can Expect

• Design and optimize analog mixed-signal layouts such as RX, TX, PLL on schematics such as RX, TX, PLL given by design team.

• Work closely with circuit designers and other teams to meet project specifications and timelines.

• Responsible for floor planning, custom layout, and verifying against design rules and schematics, including DRC, LVS, ANT, LUP, ESD, and PERC.

• Maintain detailed documentation of layout methodologies, design decisions, and verification results

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 4-7 years of related professional experience.

• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-4 years of experience.

• Proficiency in CAD tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys Custom Compiler. Virtuoso is preferred.

• Familiar with LVS, DRC, ERC, antenna, EM/IR, and ESD/LUP.

• Familiar with FinFET. Preferred if familiar with TSMC 5nm, 3nm, 2nm

• Strong communication skills.

• Ability to mentor junior engineers.

• Ability to work across teams.

Expected Base Pay Range (USD)

129,100 - 191,030, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhan