ASIC Physical Design Engineer Staff

ASIC Physical Design Engineer Staff

  

This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

   

Job Family Definition:

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.

Management Level Definition:

Contributions have visible technical impact on a product or major subcomponent.  Applies in-depth professional knowledge and innovative ideas to solve complex problems. Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs. Recognized internal authority on key technology area applying innovative principles and ideas. Provides technical leadership for significant project/program work. Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization.

Responsibilities:

• Implement physical design at the large SoC chip level from RTL to GDSII, creating a design database ready for manufacturing.
• Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level.
• Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement.
• Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, block pins placement and alignment, power grid, and RDL design, etc.
• Develop the chip-level clock network and clock stations in collaboration with clock experts.
• Budget timing among blocks and sub-chips at the chip level, generating block/chip-level static timing constraints.
• Arrange, analyze, and optimize feedthrough and repeaters among all blocks/sub-chips at the chip level.
• Perform block-level place and route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.
• Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.
• Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.
• Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.
• Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts.

Education and Experience Required:

• BS degree in electrical engineering, computer engineering, or a related field with 7+ years of experience in block or full-chip physical design, or
• MS degree in the above fields with 5+ years of related experience.

Knowledge and Skills:

• Deep design experience in large SoC designs, including IP integration, padring design, bump planning, and RDL routing strategy.
• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.
• Experience in developing and implementing power-grid and clock network at chip level.
• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.
• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.
• Exposure to 2.5D/3D packaging is preferred.
• High performance and large chip design experience is preferred.
• Exposure to DFT is preferred.
• Proficiency in writing Linux shell scr