Senior Director, Architecture Research Lab

<div class="content-intro"><p><span style="font-size: 12pt;"><strong>Please Note:</strong></span></p> <p>To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.&nbsp;</p> <p><span style="font-size: 12pt;"><strong>Advancing the World’s Technology Together</strong></span></p> <p>Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.&nbsp;</p> <p>We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.</p></div><p><span style="font-size: 12pt;"><strong><span style="font-family: arial, helvetica, sans-serif;">What You’ll Do</span></strong></span></p> <p>Lead cutting‑edge research on next‑generation AI system architectures. The role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung’s advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks.</p> <p><span style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"><strong>Location: </strong>Daily onsite presence at our <span style="color: rgb(0, 0, 0);">San Jose Headquarters</span> in alignment with our Flexible Work policy</span></p> <p><br><strong>AI System Architecture Leadership</strong></p> <ul> <li>Define system‑level architectures that solve memory‑capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems).</li> <li>Build and maintain analytical and event‑driven simulation frameworks for compute‑memory‑network performance at rack scale.</li> <li>Conduct design‑space exploration and quantitative trade‑off studies (performance, power, cost) to guide architecture decisions.</li> <li>Partner with SAIT HQ teams to align modeling insights with real‑world AI system implementations.</li> </ul> <p><strong>RISC‑V CPU Architecture Leadership</strong></p> <ul> <li>Architect high‑performance, out‑of‑order RISC‑V CPU cores that serve as host processors for AI computing systems.</li> <li>Dri