Principal Physical Design Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Principal Physical Design Engineer to work on industry-leading, high-speed, mixed-signal interface IP development as part of the SCIPS (Semi-custom and Central IP Silicon) team. The candidate should be a motivated self-starter with the ability to lead others who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

We’re committed to a diverse and inclusive workplace and encourage applicants from all background and walks of life. Difference makes us better. 

Responsibilities

• Working alongside IP architects and circuit designers to develop solutions that meet system-on-a-chip (SoC_ team requirements.
• Being responsible for all aspects of physical design including floorplanning, bump and ESD planning, synthesis, place-and-route, clock tree synthesis (CTS) and signoff for timing, electromigration & voltage drop, and physical verification.
• Integrating complex analog IPs within a digital system.
• Being a key interface between IP and SoC.
• Working with packaging engineers to understand IP requirements for 2D, 2.5D and 3D packaging options. 
• Communicatiing to coordinate and drive collaboration with RTL, DFT, CAD and SoC teams.
• Provide technical direction to less-experienced physical design engineers.
• Work with limited direction and have attention to detail.
• Provide crisp status of progress, issues, and risks on the program to the management team.
• Embody our culture and values.

Qualifications

Required Qualifications

• 9+ years of related technical engineering experience
  •  OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 9+ years of experience in hardware design.
• 6+ years of experience in RTL-to-GDS tasks such as floorplanning, bump planning, synthesis, timing closure, place-and-route, electromigration & voltage drop, and physical verification.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

• 15+ years technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
• Experience with Fusion Compiler, Primetime, Redhawk, Calibre, STAR-RCXT.
• Experience with PD for multiple clock and voltage domains IPs or subsystems.
• Experience integrating analog designs with digital, as part of a mixed-signal IP or subsystem.
• Experience in SoC-level PD, including bumps, capacitors, ESD.
• Experience in recent synthesis tool capabilities and methods for PPA improvement.
• Experience in PD signoff for timing, electromigration, and voltage drop.
• Tcl, Perl, Python, s