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Cruise is committed to building a diverse, equitable, and inclusive environment, both in our workplace and in our products. If you are looking to play a part in making a positive impact in the world by advancing the revolutionary work of self-driving cars, come join us. Even if you might not meet every requirement, we strongly encourage you to apply. You might just be the right candidate for us.

Cruise is looking for a Staff Synthesis / STA Engineer to build the next generation autonomous vehicle platforms. In this role, you will work closely with SOC Architects, RTL Designers and the Physical Design TLM to provide initial physical synthesis PPA of our custom IP and be a technical expert in synthesis, timing and power optimization, analysis and closure of high-performance and low-power complex IP and SOCs.

What you’ll be doing:

The Staff Synthesis / STA Engineer will report to the Physical Design Technical Lead Manager within the custom silicon team. You will work as part of a team to own, and be responsible for physical synthesis based PPA, managing clock definitions, writing SDC constraints, static timing analysis, constraining and debugging logic equivalence and the successful delivery of complete RTL2GDS of blocks/cores from synthesis to tape-out at high-quality as required by the custom silicon program. In addition you will be responsible for the development of methodologies to support:

• Writing and management of SDC constraint files

• Physical synthesis

• Logic equivalence

• Clock design and CTS

• DFT insertion

• RC extraction

• Timing analysis, optimization and closure

• Power analysis, optimization and closure

• Performing logical ECOs

What you must have:

• BS or MS in Engineering or a related discipline or equivalent combination education.

• 15+ years of professional hands-on experience in synthesis / static timing analysis / timing closure of high performance designs with frequencies > 1 Ghz

• Strong expertise with writing SDC constraints, physical synthesis, logic equivalence, DFT insertion, RC-extraction, timing closure, static timing analysis, power analysis, ECOs, using any of the current generation of design tools (Design Compiler, Formality, Star-RCXT, PrimeClosure, PrimeTime, PrimePower, RedHawk, Genus, LEC, Cerberus, Certus, Voltus, Tempus, Quantus)

• Proven tape-outs of large, complex SoCs with multiple clock domains using FinFet and/or GAA based technology nodes (16FFC/N7/N5/N3/N2)

• Strong scripting skills using TCL, PERL, Python, Makefiles, shell scripting

• Experience with standard HDL languages (VHDL, Verilog, System Verilog)

• Experience creating automated physical design methodologies

• Excellent communication and documentation skills and be willing to travel

Bonus points!

• Experience with the following: block-level floorplanning, power grid design, hard macro / SRAM placement, clock design and CTS, place and route, physical verification using any of the current generation of design tools (Innovus, ICC2, Fusion Compiler, IC-Validator, Pegasus, Calibre-LVS, Calibre-DRC)

• Experience completing physical design of high speed memory (DDR, LPDDR, HBM) and SERDES based interfacing subsystems. (PCIe, USB, 1G/10G/25G Ethernet)

• Experience completing physical design of high-performance compute cores (ARM A-class CPUs, RISC-V CPUs, DSPs, GPUs , NPUs)

• Experience with Design For Test and Design for Debug tools and architectures

• Experience with automotive and safety critical applications including ISO 26262

• Experience developing AI-based physical design flows

The salary range for this position is $170,000 - 250,000. Compensation will vary depending on location, job-related knowledge, skills, and experience. You may also be offered a bonus, restricted stock units, and benefits. These ranges are subject to change.

Why Cruise?

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