Principal Technical IP Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Hardware Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering is the center hub providing IP to be used by all BUs across Marvell. In this role, you’ll be part of the the internal Marvell team that manages 3rd party IP management and will work to source IP from external IP suppliers. In this internal role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and you will engage all parts of Marvell including the SoC architecture teams, Business development, Legal, Finance, Sales, and support critical Hyperscalar programs that heavily leverage DDR/LPDDR/HBM Interface IP, that is predominantly 3rd party IP.

What You Can Expect

Looking for a talented Principal Technical IP Engineer to join the Marvell Team to manage 3rd party IP integration engineers to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients.

Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, automotive, hyper-scaler, communications, and storage. As member of the Marvell team to manage 3rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation. 

You will assist sales in winning bids by working with leading edge IP providers to meet customer requirements.  You will manage 3rd party developers in completing core designs and providing required design rules.  You will advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider.  Post-silicon validation at customer sites will require a limited degree of travel.  

Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution. You will assist with 8D follow-through for significant supplier issues.

What We're Looking For

• BS degree in technical discipline with minimum 7 years of relevant experience. 
• Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging. 
• Proficient in project management tasks required to manage 3rd party developers.  
• Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking 
• Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing 
• Good communication and customer manage