Job Details:

Job Description: 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below.

Life at Intel

Diversity at Intel

Join the Network and Edge Group (NEX) as a Principal Engineer – DFT  to plan, develop and sell infrastructure acceleration solutions using Infrastructure Processing Units (IPU) in the Cloud, Telco and Enterprise market segments.

Responsibilities will include, but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
• Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

The ideal candidate will have the following skills in addition to the qualifications listed below:

• Experience in project management with organizational skills and a track record for delivering a set of objectives on schedule and within budget.
• Must be a team player, with a demonstrated experience technically influencing others.
• Strong problem-solving skills.
• Excellent communication skills.

Qualifications:

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

• Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field and 10+ years of relevant experience.

• 4+ years’ experience DFT experience

• 6+ years experience with standard industry tools.

• 6+ years experience with Silicon design such as ASIC/CPU/Custom design and testability.

• 6+ years experience with Scan design, ATPG methodology and commercial EDA tools, including:

Scan planning

Compression logic generation and insertion

STA and Test constraints

Test and pattern generation and validation.

• 3+ years experience with logical and physical design (PD) processes.

Preferred Qualifications:

• Master’s degree or higher.

• 5+ years with Tessent.

• SoC silicon experience.

• Fault simulation and Fault analysis, diagnostic capabilities.

• Clock architecture

• Experience with scripting languages, Linux/Unix environment.

• Strong understanding of small delay defect test models for current technology nodes, including Stuck At, Transition, Cell Aware, Bridging, etc.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or sch