IC Validation Engineer Intern - Masters Degree

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell DCE group is looking for an electrical engineering intern in the greater Los Angeles, CA
office. The qualified candidate will work with a team of energetic, technically strong, multi-disciplined
engineering team in the development of critical components for 800G, 1.6T ZR high speed optical
communication systems that will enable the next generation cloud computing that powers the today's
AI landscape.

The successful candidate will be part of the Optics team responsible for validation of Analog front
end design used in various physical medium devices, Photonics Integrated circuits, board-level
hardware design, test development in microwave test and measurement at mmWave and beyond,
and scripting of automatic test systems for testing hardware with specific firmware.

The candidate will be offered the opportunity to grow and be exposed to a broad range of
engineering skills & responsibilities over time.

What You Can Expect

A student intern may be assigned any related to designing a test interface, probe solution, test
automation, PIC test development, testing of CDSP SerDes, SiGe BiCMOS transimpedance
amplifiers and laser drivers. This may include system modeling, block design, simulation, or lab
measurement. Assignments will depend on the skills and interests of the student intern as well as
the project phase.
 Detailed responsibilities can be:

• Develop Hardware for Chip level and/or sub-system level performance evaluation/validation.
• Initial work will involve in execution of engineering validation plan for Optoelectronic components (TIAs & modulator Drivers)
• Learn to understand the Spec and functionalities of Marvell Optoelectronics products
• Designing hardware platform for validating chips and system with Senior member’s guidance
• Coding/scripting to automate measurements in Python
• Verify and Trouble shoot board level or chip level design.
• Engage and collaborate among validation team members for test development, data base structure, test hardware (Probes wedges, probes cards, and PCB,) and performing assigned validation projects.
• Documentation of design/validation results and report generations

Being successful during internship could potentially earn as a Post Silicon Validation Engineer role
and overtime, design and innovate hardware/software and test/validation methodologies.

• Solving low noise- high gain amplifier testing up to mmWave.

What We're Looking For

- Candidate MUST be currently pursuing a MS degree in CE/EE or related technical field(s) at ABET accredited University.

- Strong fundamentals in at least 2 to 3 of the following areas:

• RF and Microwave Engineering (S-parameters.) & Devices (Filters, Splitters/ Combiners, Travelling wave amplifiers)
• Transistor-level Analog design
• Common building blocks & functions: OpAmps, Digital logic
• Communication Theories – modulations, noise, SNR, digital signal processing, equalization techniques, Q-factor, BER
• Digital System engineering – signaling and synchronization.
• Programming: Python, C, etc. (Exposures to Matlab and ADS is desirable)
• Silicon Photonics

- Team player with good communication skills.

- Enjoys hands on lab work using test and measurement equipment (VNA, Oscilloscope, Spectrum analyzer, and in circuit emulator.)

Expected Base Pay Range (USD)

27 - 53, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role