Sr. Memory Controller Micro-Architect/Logic Designer

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Sr. Memory Controller Micro-Architect/Logic Designer, you will contribute to the micro-architecture development and logic design of custom Memory controller IP. This is a senior level role where you will interact with the system architects, verification, performance/power, and design implementation teams to drive the RTL design, performance and power optimization, logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

Key responsibilities include:

• You drive the timely development of custom memory controller blocks
• You engage with the architects and help define next-generation Samsung memory controller
• You handle microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• You work with the verification team to verify the functionality and correctness of the design
• You collaborate with implementation to achieve your timing and area
• You produce quality RTL on schedule meeting PPA goals
• You interact with performance and power team on achieving performance and power goals
• You partner with the physical design and CAD team to resolve implementation level details

Skills and Qualifications

Minimum Requirements:

• BS or MS in Computer Engineering or related plus over 10 years of relevant experience
• Deep understanding of memory controller is a must have, along with PHY design and experience in one or more memory technologies: DDR4/5, LPDDR & HBM
• Strong background owning and driving the RTL design of various sub-blocks of memory controller for the high-performance digital designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
• Experience with a scripting languages like Perl or Python
• Knowledge of Arm CHI/ACE/AXI coherent interconnect and bus protocols
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team

Preferred candidate will possess the following:

• PhD in Computer Engineering or related plus 7 years of relevant experience
• Proficient in AMBA protocol
• Energetic, curiosity, and passion in logic design
• Efficient digital design techniques
• Knowledge of JEDEC memory standards

Our Team

We’re building a new team to influence the product roadmap for a market-leading system IP solution. Our team focuses on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem. 

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments. 

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture. 

Pay Transparency

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,557 and $305,414. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (af