R&D Engineering, Architect- 3DIC and Advanced Packaging SIPI

General Information

Job Title R&D Engineering, Architect- 3DIC and Advanced Packaging SIPI Job ID 9735 City Hillsboro State/Province Oregon Date Posted 25-Feb-2025 Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee Remote Eligible No Base Salary Range: $171000 - $256000

Descriptions & Requirements

Job Description and Requirements

Synopsys is looking for a 3DIC and Advanced Packaging SIPI architect who will perform SIPI analysis for TSV impact to EMIR, HSIO interference, T-coil performance degradation, and other electrical performance impact to IP and SOC. Work with engineers to do 3DIC design partition, floor planning, TSV placement, mockup design, and silicon interposer/bridge design for Synopsys IP, test chip, and chiplet to meet electrical requirement and optimize for thermal performance, come up with design guidelines and best practice, and help customers explore their solution space. Candidates with solid understanding of silicon design, advanced packaging, power grid design, and strong SIPI experience are required. Can-do attitude, quick learning, and solid electronic skills are assets. You will be working with a global, highly skilled and very supportive team. 

 

Responsibilities 

• Conducting TSV to TSV coupling, TSV interference to HSIO and SRAM study
• Analyzing T-coil coupling and performance degradation with 3DIC stacking study
• Leading 3DIC design partition, floor planning, IP placement, TSV placement, power grid planning and design
• Performing Power and EMIR analysis, design optimization
• Managing Bump map pin assignment and AP RDL design
• Advanced packaging interposer electrical design, optimization, and post-layout model extraction, end to end simulation
• Conducting eDTC partitioning and PI analysis and generating Design guideline and best practice generation
• Creating IP and chiplet Pre-sales P&R mockup design, simulation and post-sales support
• Interface with Synopsys EDA tool and internal CAD group to build 3DIC and 2.5D design flow

   

Requi