Senior Member of Technical Staff (90980)

Responsible for the architectural and micro-architectural understanding of variousblocks of a hardware accelerated device. Develop a System Verilog testbench andstimulus to run and check the design under test. Define and measure coverage toensure that the stimulus is covering the architectural and micro-architectural designspace. Use simulation and emulation platforms to run the design. The checkingenvironment involves the integration of the reference model in the testbench. Thecheckers should be able to identify the faulty part of the design and report errors.Debug fails and root cause the failure to a specific RTL problem. Develop a testing planthat is comprehensive and deploys the use of checkers. Develop a formal basedverification bench to check if the design statements and properties hold true.

Education:

• Master’s or foreign equivalent in Electrical Engineering or related field

Experience:

• 2 years of experience in job offered or related occupation.

Special Requirements: Must have at least 1 year of prior work experience in each of the following:

• 1. Understand the architecture & micro architecture details of how a general purpose
• processor / CPU works. Understand the memory consistency model of the design.
• 2. Build block level environments, write testplans, measure the coverage.
• 3. Generate / write tests in assembly level language, system verilog.
• 4. Develop end to end checkers.
• 5. Experience with the formal verification flow.
• **Telecommuting allowed for this position**

Worksite: 3315 Scott Blvd., Fl. 4, Santa Clara, CA 95054 Applicant Instructions:Include job code 90980 in reply. EOE.