Jobs and Careers

Principal Microelectronics Engineer

Annapolis Junction, MD, United Statesfull_timeVerifiedPosted 14 Oct 2025

About the role

Job ID: TAP00113
Position: Principal Microelectronics Engineer
Location: US - Maryland, DC, Virginia (Partial Telework)
Category: Hardware
Clearance Requirement: None (U.S. Citizenship required)
Education Requirement: BS in Electrical Engineering (or related technical field)
Experience Requirement: 10+ Years

TAP is seeking to hire a Principal Microelectronics Engineer to join our team! If you are a highly motivated engineer who enjoys a challenging and dynamic environment where your contributions are both critical and valued, this company will provide you with the tools and opportunity to thrive.

The Principal Microelectronics Engineer will be working alongside the Department of Commerce National Institute of Standards and Technology (DOC NIST) in planning and executing microelectronics programs related to the CHIPS and Science Act. The successful candidate will work closely with a small team of interdisciplinary, inter-agency technical subject matter experts (SMEs) and program managers in collaboration with industry and academia to strengthen the domestic microelectronics supply chain. The Principal Microelectronics Engineer will work to shape, write, release, assess, and award industry Notice of Funding Opportunities (NOFOs). And, once awarded, they will support the execution and management of the resulting programs (managing scope, cost, schedule, risk, resources, etc.). This position requires an individual with both technical and program management skills.

Required Qualifications (Must Have’s):

U.S. Citizenship
Ability and willingness to obtain a Public Trust clearance.
Bachelors Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, Materials Science, Physics, Computer Science or related technical discipline.
10+ years of experience
- A relevant Masters Degree may be substituted for 2 years of experience (MS w/ 8+ years)
- A relevant PhD Degree may be substituted for 4 years of experience (PhD w/ 6+ years)
Excellent verbal and written communication skills.
- This position requires the ability to brief senior-level executives within the government, industry and academia.
- The successful candidate will have the ability to write and review technical documents.
Microelectronics hardware subject matter expertise in at least one of the areas listed below:
- Materials & Substrates: Experience with fabrication projects utilizing organics, glass, and semiconductor-based materials such as those found in advanced PCB, fan-out wafer level packaging, and or SIP device fabrication. Embedded components, laminated films such as ABF, spun-on films such as BCB, as well as copper metallization techniques.
- Equipment, Tools & Processing: First-hand knowledge of semiconductor and printed circuit board equipment designed for handling large-area substrates such as 200/300MM rounds, or greater than 500MM panels. Prior tool selection and or user experience in these areas a plus.
- Power Delivery & Thermal Management: Experience on projects utilizing TSV device fabrication techniques to deliver backside power delivery to Integrated Circuit designs such as chemical mechanical planarization (CMP), dielectrics deposition, atomic layer deposition (ALD), and metals deposition.
- Connectors & Photonics: Experience with optical I/O methodologies to bring signals on-chip, using fiber and or waveguides, to reach over 1 Tbps/mm full-duplex I/O density. Experience in linear drive optics projects a plus.
- Codesign & EDA: Experience executing or managing design projects that utilized Electronic Design Automation (EDA) tools such as Ansys, Cadence Allegro, Cadence Virtuoso, Keysight Technologies, Siemens formerly Mentor Graphics, Calibre, Expedition, Synopsys, Xilinx Vivado, Intel Quartus Prime, Microsemi Libero, and or Lattice Diamond.
- Chiplets: Experience in device design decisions and trade studies for make-buy decisions involving disaggregation of monolithic designs into chiplet architectures, experience or deep knowledge of the UCIe Standard, AIB, SERDES, and other methods of chip-to-chip communications.